Method for forming an on-chip high frequency electro-static discharge device
US7759243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jan 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.