Selective formation of dielectric etch stop layers
US7759262B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jun 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods to selectively form a dielectric etch stop layer over a patterned metal feature. Embodiments include a transistor incorporating such an etch stop layer over a gate electrode. In accordance with certain embodiments of the present invention, a metal is selectively formed on the surface of the gate electrode which is then converted to a silicide or germanicide. In other embodiments, the metal selectively formed on the gate electrode surface enables a catalytic growth of a silicon or germanium mesa over the gate electrode. At least a portion of the silicide, germanicide, silicon mesa or germanium mesa is then oxidized, nitridized, or carbonized to form a dielectric etch stop layer over the gate electrode only.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.