Semiconductor device
US7759714B2 · kind B2 · utility
119Cited by
0References
15Claims
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Assignee
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Key dates
| Filing date | Jun 26, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jan 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed and low-voltage DRAM memory cell capable of operating at 1 V or less and an array peripheral circuit are provided. A DRAM cell is comprised of a memory cell transistor and planar capacitor which utilize a FD-SOI MOST structure. Since there is no junction leakage current, loss of stored charge is eliminated, and the low-voltage operation can be realized. Further, a gate and a well in a cross-coupled type sense amplifier using FD-SOI MOSTs are connected. By this means, a threshold value dynamically changes and high-speed sensing operation can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.