Power safe translation table operation in flash memory
US7761740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jan 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.