Integrated circuit and a method for designing a boundary scan super-cell
US7761760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2005 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jul 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for designing an integrated circuit, the method includes: providing an initial definition of a boundary scan register that includes identical super-cells adapted to be connected to multiple pin types; and determining the configuration of each super-cell by providing at least one pin type indication signal to each super-cell. An integrated circuit that includes a boundary scan super-cell, the boundary scan super-cell includes first circuitry adapted to be connected to at least one type of integrated circuit pin; characterized by further including a second circuitry, connected to first circuitry, wherein the second circuitry is adapted to receive at least one pin type indication signal and in response allows the boundary scan super-cell to be connected to at least one additional type of an integrated circuit pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.