Method of manufacturing a transistor and memory cell array

US7763514B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Johannes von Kluge · Dresden, DE
• Stefan Tegen · Dresden, DE

Key dates

• Filing date: Sep 7, 2007
• Grant date: Jul 27, 2010
• Expiry date: May 30, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

A transistor of an integrated circuit includes a first and second source/drain regions, a channel region connecting the first and second source/drain regions, and a gate electrode configured to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, that is defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, wherein the depth d1 is measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate in a distance to the top surface that is less than the depth d1.