Stefan Tegen
53Patents
4h-index
39Co-inventors
62Inventor score
Filing activity: May 2, 2005 → Oct 16, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7659602B2 | Semiconductor component with MIM capacitor | Electricity | 8 | Active |
| US7851356B2 | Integrated circuit and methods of manufacturing the same | Electricity | 7 | Active |
| US7371645B2 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device | Electricity | 6 | Expired |
| US7291532B2 | Low resistance contact in a semiconductor device | Electricity | 4 | Expired |
| US8987090B2 | Method of manufacturing a semiconductor device with device separation structures | Electricity | 4 | Active |
| US7763514B2 | Method of manufacturing a transistor and memory cell array | Electricity | 3 | Active |
| US8980714B2 | Semiconductor device with buried gate electrode structures | Electricity | 3 | Active |
| US7473952B2 | Memory cell array and method of manufacturing the same | Electricity | 2 | Expired |
| US9107335B2 | Method for manufacturing an integrated circuit and an integrated circuit | Emerging Cross-Sectional Technologies | 2 | Active |
| US8284596B2 | Integrated circuit including an array of diodes coupled to a layer of resistance changing material | Physics | 2 | Active |
| US9209248B2 | Power transistor | Electricity | 2 | Active |
| US10020387B2 | Method for manufacturing a bipolar junction transistor | Electricity | 1 | Active |
| US8013377B2 | Method for producing an integrated circuit and arrangement comprising a substrate | Electricity | 1 | Active |
| US9368408B2 | Method of manufacturing a semiconductor device with buried channel/body zone and semiconductor device | Electricity | 1 | Active |
| US7777266B2 | Conductive line comprising a capping layer | Electricity | 1 | Active |
| US7804708B2 | Integrated circuit including an array of memory cells and method | Physics | 1 | Active |
| US9812369B2 | BiMOS device with a fully self-aligned emitter-silicon and method for manufacturing the same | Electricity | 1 | Active |
| US7439125B2 | Contact structure for a stack DRAM storage capacitor | Electricity | 1 | Active |
| US7456086B2 | Semiconductor having structure with openings | Electricity | 1 | Active |
| US10290735B2 | Methods of manufacturing a semiconductor device with a buried doped region and a contact structure | Electricity | 0 | Active |
| US9876105B2 | Semiconductor device with buried doped region and contact structure | Electricity | 0 | Active |
| US10672895B2 | Method for manufacturing a bipolar junction transistor | Electricity | 0 | Active |
| US9941375B2 | Method for manufacturing a semiconductor device having silicide layers | Electricity | 0 | Active |
| US11824114B2 | Transistor device having a field plate in an elongate active trench | Electricity | 0 | Active |
| US9984930B2 | Method for processing a carrier | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.