Patent · US Active

Method and structure to process thick and thin fins and variable fin to fin spacing

US7763531B2 · kind B2 · utility

66Cited by
9References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 29, 2007
Grant dateJul 27, 2010
Priority date
Expiry dateAug 29, 2027

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/2831
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.