Multi-time programmable memory
US7763928B2 · kind B2 · utility
4Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2007 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Mar 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.