Post last wiring level inductor using patterned plate process
US7763954B2 · kind B2 · utility
5Cited by
21References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2008 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Jul 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.