Clock distribution network supporting low-power mode
US7764095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2008 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | May 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a clock network. Clock distribution may be disabled as needed to save power. The first feedback loop is active irrespective of whether clock distribution is enabled. The delay through the clock network may drift due to temperature and supply-voltage fluctuations, which introduces phase errors in the distributed clock signals. A second feedback loop is activated when clock distribution is enabled to compensate for this drift.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.