Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
US7765338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2007 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Jul 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FET computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.