Multi-node system in which home memory subsystem stores global to local address translation information for replicating nodes
US7765381B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2004 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | May 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include a plurality of nodes. Each node may include an active device and a memory subsystem coupled to the active device. An active device in one of the nodes is configured to generate a global address that identifies a coherency unit and associated translation information identifying a translation function to be performed on the global address. A memory subsystem included in the node is configured to perform the translation function identified by the translation information on the global address to generate a physical address of the coherency unit within the memory subsystem. An additional memory subsystem included in an additional one of the nodes is configured to store the translation information identifying the translation function used in the node. In response to a request for access to the coherency unit, the additional memory subsystem is configured to send the translation information to the node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.