Sub-lithographic interconnect patterning using self-assembling polymers
US7767099B2 · kind B2 · utility
67Cited by
12References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Apr 4, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to the formation of sublithographic features in a semiconductor structure using self-assembling polymers. The self-assembling polymers are formed in openings in a hard mask, annealed and then etched, followed by etching of the underlying dielectric material. At least one sublithographic feature is formed according to this method. Also disclosed is an intermediate semiconductor structure in which at least one interconnect wiring feature has a dimension that is defined by a self-assembled block copolymer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.