Method for repairing errors of patterns embodied in thin layers
US7767104B2 · kind B2 · utility
0Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2004 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Dec 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A fabrication method in thin layers, for example of integrated electronic circuits or MEMS. A correction method allows design errors made for example by photolithography in a thin layer to be repaired, and without necessarily having to utilize a new mask or without having to correct an erroneous mask. A lithography device allows certain of operations of such a method to be employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.