Method of forming a silicide layer on a thinned silicon wafer, and related semiconducting structure
US7767563B2 · kind B2 · utility
4Cited by
3References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Oct 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconducting structure includes a thinned silicon substrate (110), a silicide layer (120) over the thinned silicon substrate, a metal layer (130) over the silicide layer, a solder interface layer (140) over the metal layer, and a cap layer (150) over the solder interface layer. The thinned silicon substrate is no thicker than approximately 500 micrometers. The silicide layer is formed using a rapid thermal processing procedure that locally heats the interface between the metal layer and the silicon substrate but causes no more than negligible thermal impact to other areas of the silicon wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.