Multiple conduction state devices having differently stressed liners

US7768041B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Dureseti Chidambarrao · Weston, US
• David M. Onsongo · Austin, US

Key dates

• Filing date: Jun 21, 2006
• Grant date: Aug 3, 2010
• Expiry date: Feb 1, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/938

Abstract

A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.