David M. Onsongo
13Patents
4h-index
21Co-inventors
56Inventor score
Filing activity: Jun 7, 2005 → Oct 7, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7337420B2 | Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models | Electricity | 41 | Expired |
| US8354678B1 | Structure and method for forming a light detecting diode and a light emitting diode on a silicon-on-insulator wafer backside | Electricity | 13 | Active |
| US7560326B2 | Silicon/silcion germaninum/silicon body device with embedded carbon dopant | Electricity | 12 | Active |
| US7242239B2 | Programming and determining state of electrical fuse using field effect transistor having multiple conduction states | Physics | 6 | Expired |
| US7123529B1 | Sense amplifier including multiple conduction state field effect transistor | Physics | 4 | Expired |
| US8451021B1 | Calibrating on-chip resistors via a daisy chain scheme | Electricity | 3 | Active |
| US9710577B2 | Heat source integration for electromigration analysis | Physics | 3 | Active |
| US8405165B2 | Field effect transistor having multiple conduction states | Electricity | 1 | Active |
| US8222702B2 | CMOS diodes with dual gate conductors, and methods for forming the same | Electricity | 0 | Active |
| US7768041B2 | Multiple conduction state devices having differently stressed liners | Emerging Cross-Sectional Technologies | 0 | Active |
| US7737500B2 | CMOS diodes with dual gate conductors, and methods for forming the same | Electricity | 0 | Active |
| US9405311B1 | Bias-temperature induced damage mitigation circuit | Electricity | 0 | Active |
| US9401643B1 | Bias-temperature induced damage mitigation circuit | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.