Suppressing ringing in high speed CMOS output buffers driving transmission line load
US7768311B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Aug 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/0822
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.