Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices
US7768812B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Aug 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.