Method and system for preventing noise disturbance in high speed, low power memory
US7768866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2006 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | May 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a memory cell and a sense amplifier which has a sensing interval. An output circuit is coupled to the sense amplifier and responsive to a clock signal to accept the signal from the sense amplifier. A first source of timing signals generates a first timing signal in response to an enable signal which is asynchronous relative to the clock signal. A second source of timing signals generates a second timing signal based on the clock signal. A switch selects one of the first and second timing signals at the timing signals for use to define pre-charge and sensing intervals for the sense amplifier. The first source of timing signals is selected during an interval of time corresponding to a clock latency, so that the timing signals define a sensing interval where transitions in the clock signal are outside of the sensing interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.