Dual-issuance of microprocessor instructions using dual dependency matrices
US7769984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Sep 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.