Method for cache correction using functional tests translated to fuse repair
US7770067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Dec 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.