Trench forming method and structure

US7772083B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Alan B. Botula · South Burlington, US
• Michael L. Gautsch · Jericho, US
• Alvin J. Joseph · Williston, US
• Max G. Levy · South Burlington, US
• James A. Slinkman · Montpelier, US

Key dates

• Filing date: Dec 29, 2008
• Grant date: Aug 10, 2010
• Expiry date: Jan 31, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76283
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.