Implant damage of layer for easy removal and reduced silicon recess
US7772094B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Dec 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.