Patent · US Active

Performance enhanced silicon-on-insulator technology

US7772648B1 · kind B1 · utility

20Cited by
2References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 12, 2007
Grant dateAug 10, 2010
Priority date
Expiry dateOct 20, 2027

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/201

Abstract

The present invention includes a silicon-on-insulator (SOI) wafer that enhances certain performance parameters by increasing silicon device layer and insulator layer thicknesses and increasing silicon handle wafer resistivity. By increasing the silicon device layer thickness, effects of the floating body problem may be significantly reduced. By increasing the insulator layer thickness and the silicon handle wafer resistivity, influences from the silicon handle wafer on devices formed using the silicon device layer may be significantly reduced. As a result, standard tools, methods, and processes may be used.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.