Performance enhanced silicon-on-insulator technology
US7772648B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Oct 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
The present invention includes a silicon-on-insulator (SOI) wafer that enhances certain performance parameters by increasing silicon device layer and insulator layer thicknesses and increasing silicon handle wafer resistivity. By increasing the silicon device layer thickness, effects of the floating body problem may be significantly reduced. By increasing the insulator layer thickness and the silicon handle wafer resistivity, influences from the silicon handle wafer on devices formed using the silicon device layer may be significantly reduced. As a result, standard tools, methods, and processes may be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.