Shielded gate trench FET with multiple channels
US7772668B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | May 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A field effect transistor (FET) includes a pair of trenches extending into a semiconductor region. Each trench includes a first shield electrode in a lower portion of the trench and a gate electrode in an upper portion of the trench over but insulated from the shield electrode. First and second well regions of a first conductivity type laterally extend in the semiconductor region between the pair of trenches and abut sidewalls of the pair of trenches. The first and second well regions are vertically spaced from one another by a first drift region of a second conductivity type. The gate electrode and the first shield electrode are positioned relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.