Method and system for collecting alignment data from coated chips or wafers
US7773220B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Aug 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01076
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process and system for determining alignment data for partially obscured features on wafers or chips when a wafer or chip is substantially coated by an over bump applied material, e.g. a resin or film, and using that data to align the wafers or chips for subsequent operations such as dicing or joining. Position data for alignment is produced by identifying a location of an at least partially obscured feature by varying the depth of focus upon a work piece to determine an SNR approximating a maximum value from an image captured by optical scanning. An SNR above a threshold value can be employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.