8T low leakage SRAM cell
US7773407B2 · kind B2 · utility
14Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2008 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Oct 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters connected between a positive supply voltage (Vcc) and a first node, a first NMOS transistor with a gate and drain connected to the first node and a source connected to a ground, and a second NMOS transistor with a drain and source connected to the first node and the ground, respectively, and a gate connected to a control-line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.