Design structure for improved memory column redundancy scheme
US7773437B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | May 7, 2008 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Feb 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in machine readable medium used in a design process includes a system for implementing a memory column redundancy scheme. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.