Method and apparatus for reducing dynamic power in a system
US7774729B1 · kind B1 · utility
3Cited by
4References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 29, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Oct 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes inserting sequential elements into combinatorial logic bounded by a source sequential element and a destination sequential element to reduce glitching. The sequential elements are clocked with a clock signal having a phase difference from at least one of a clock signal clocking the source sequential element and the destination sequential element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.