Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same
US7776657B2 · kind B2 · utility
3Cited by
4References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 6, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Nov 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16152
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.