Methods for forming an integrated circuit, including openings in a mold layer from nanowires or nanotubes

US7776759B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Peter Lahnor · Dresden, DE
• Odo Wunnicke · Dresden, DE
• Johannes Heitmann · Dresden, DE
• Peter Moll · Dresden, DE
• Andreas Orth · Friedrichsdorf, DE

Key dates

• Filing date: Mar 16, 2007
• Grant date: Aug 17, 2010
• Expiry date: Feb 1, 2028

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/72

Abstract

A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.