Peter Lahnor
12Patents
3h-index
27Co-inventors
56Inventor score
Filing activity: Jan 27, 2000 → Jan 31, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6153492A | Method for improving the readability of alignment marks | Electricity | 13 | Expired |
| US6695687B2 | Semiconductor substrate holder for chemical-mechanical polishing containing a movable plate | Performing Operations; Transporting | 7 | Expired |
| US7894240B2 | Method and apparatus for reducing charge trapping in high-k dielectric material | Physics | 4 | Active |
| US6689691B2 | Method of simultaneously polishing a plurality of objects of a similar type, in particular silicon wafers, on a polishing installation | Electricity | 2 | Expired |
| US6932674B2 | Method of determining the endpoint of a planarization process | Performing Operations; Transporting | 2 | Expired |
| US7776759B2 | Methods for forming an integrated circuit, including openings in a mold layer from nanowires or nanotubes | Emerging Cross-Sectional Technologies | 2 | Active |
| US8138538B2 | Interconnect structure for semiconductor devices | Electricity | 1 | Active |
| US6787431B2 | Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers | Emerging Cross-Sectional Technologies | 0 | Expired |
| US10530273B2 | Unfolding bridge, inverter having reactive-power capability, and polarity reversing method | Emerging Cross-Sectional Technologies | 0 | Active |
| US6821894B2 | CMP process | Electricity | 0 | Expired |
| US6827635B2 | Method of planarizing substrates | Performing Operations; Transporting | 0 | Expired |
| US6893968B2 | Defect-minimizing, topology-independent planarization of process surfaces in semiconductor devices | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.