Random access memory device utilizing a vertically oriented select transistor
US7777264B2 · kind B2 · utility
12Cited by
15References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Feb 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.