Stacked microelectronic layer and module with three-axis channel T-connects
US7777321B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Oct 25, 2005 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Jul 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for interconnecting stacked layers containing integrated circuit die and a device built from the method is disclosed. The stacked layers are bonded together to form a module whereby individual I/O pads of the integrated circuit die are rerouted to at least one edge of the module. The rerouted leads terminate at the edge. Channels are formed in a surface of the module or on the surface of a layer whereby the rerouted leads are disposed within the channel. The entire surface of the edge or layer is metalized and a predetermined portion of the metalization removed such that the rerouted leads within each channel are electrically connected to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.