Circuit protection system
US7777996B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Aug 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.