Operation analysis method of semiconductor integrated circuit
US7779376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2007 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Jul 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation analysis is performed for a semiconductor integrated circuit designed by using substrate bias control technology. Power supply potential and substrate potential are analyzed by using circuit information of the semiconductor integrated circuit, and from obtained power supply potential waveform information and substrate potential waveform information, potential difference information indicating a difference value between the power supply potential and the substrate potential is obtained. On the basis of this potential difference information, effects on circuit delay due to substrate noise are analyzed using a delay library showing a relationship between the difference value and the effects on circuit delay. Further, a determination is performed as to whether the difference value exceeds a predetermined difference restriction value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.