Test generation for low power circuits
US7779381B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2006 |
| Grant date | Aug 17, 2010 |
| Priority date | — |
| Expiry date | Mar 5, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing. By automatically partitioning the faults to remove those that cannot be excited or observed during manufacturing and testing, the testability of the device in terms of its partitions or parts will accurately reflect the power state of the logic portions of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.