Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby
US7781260B2 · kind B2 · utility
11Cited by
3References
14Claims
0Family size
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Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Nov 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and associated structures of forming microelectronic devices are described. Those methods may include coating an interconnect structure disposed on a die with a layer of functionalized nanoparticles, wherein the functionalized nanoparticles are dispersed in a solvent, heating the layer of functionalized nanoparticles to drive off a portion of the solvent, and applying an underfill on the coated interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.