Method for producing mixed stacked structures, different insulating areas and/or localised vertical electrical conducting areas
US7781300B2 · kind B2 · utility
10Cited by
21References
74Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2005 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Oct 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for producing a semiconducting structure including:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.