System and method for filling vias
US7781311B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2006 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Oct 31, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
System and method for filling vias in integrated circuits A preferred embodiment comprises forming a spacer layer on a substrate, forming a via with walls and a bottom in the spacer layer, depositing a conformal conductive layer on the spacer layer and on the walls and bottom of the via, spinning-on a photo-definable material on the conductive layer, forming a fill layer on the conductive layer and filling the via, exposing portions of the fill layer to an exposing light using a photomask, developing the fill layer to remove select portions of the fill layer and leave a portion of the fill layer filling the via, and removing the spacer layer. The use of a spin-on photo-definable material increases the material's filling and planarizing capabilities, while enabling a reduction in the number of process steps, which may reduce the likelihood of manufacturing defects, thereby increasing manufacturing yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.