Interconnect structure and method of fabricating same
US7781892B2 · kind B2 · utility
9Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2005 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Oct 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved interconnect structure and method of making such a device. The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.