Su Chen Fan
118Patents
10h-index
117Co-inventors
83Inventor score
Filing activity: Oct 13, 1999 → Sep 21, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8084311B1 | Method of forming replacement metal gate with borderless contact and structure thereof | Emerging Cross-Sectional Technologies | 36 | Active |
| US9257348B2 | Methods of forming replacement gate structures for transistors and the resulting devices | Electricity | 31 | Active |
| US8772168B2 | Formation of the dielectric cap layer for a replacement gate structure | Electricity | 25 | Active |
| US8679968B2 | Method for forming a self-aligned contact opening by a lateral etch | Electricity | 18 | Active |
| US9397049B1 | Gate tie-down enablement with inner spacer | Electricity | 15 | Active |
| US10020381B1 | Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors | Electricity | 11 | Active |
| US9570573B1 | Self-aligned gate tie-down contacts with selective etch stop liner | Electricity | 11 | Active |
| US8383490B2 | Borderless contact for ultra-thin body devices | Electricity | 11 | Active |
| US7371663B2 | Three dimensional IC device and alignment methods of IC device substrates | Electricity | 11 | Active |
| US8679909B2 | Recessing and capping of gate structures with varying metal compositions | Electricity | 10 | Active |
| US9728462B2 | Stable multiple threshold voltage devices on replacement metal gate CMOS devices | Electricity | 10 | Active |
| US7781892B2 | Interconnect structure and method of fabricating same | Electricity | 9 | Active |
| US8124525B1 | Method of forming self-aligned local interconnect and structure formed thereby | Electricity | 8 | Active |
| US9293551B2 | Integrated multiple gate length semiconductor device including self-aligned contacts | Electricity | 8 | Active |
| US9576901B1 | Contact area structure and method for manufacturing the same | Electricity | 8 | Active |
| US8957465B2 | Formation of the dielectric cap layer for a replacement gate structure | Electricity | 7 | Active |
| US9455254B2 | Methods of forming a combined gate and source/drain contact structure and the resulting device | Electricity | 7 | Active |
| US9385123B2 | STI region for small fin pitch in FinFET devices | Electricity | 6 | Active |
| US9570397B1 | Local interconnect structure including non-eroded contact via trenches | Electricity | 5 | Active |
| US8796783B2 | Borderless contact structure employing dual etch stop layers | Electricity | 5 | Active |
| US6254739A | Pre-treatment for salicide process | Chemistry; Metallurgy | 5 | Expired |
| US9583442B2 | Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer | Electricity | 5 | Active |
| US11171051B1 | Contacts and liners having multi-segmented protective caps | Electricity | 4 | Active |
| US10943990B2 | Gate contact over active enabled by alternative spacer scheme and claw-shaped cap | Electricity | 4 | Active |
| US10832943B2 | Gate contact over active region with self-aligned source/drain contact | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.