Apparatus and method for memory cell power-up sequence
US7782702B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2008 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Feb 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided to enhance the power-up sequence for integrated circuits (ICs) that contain memory cells having single-ended data inputs with no local reset function. During a power-up sequence, the logic levels that are applied to the data, address, and power inputs of the memory cell are restricted to particular magnitudes by a power-on reset (POR) state machine. First, the data input of the memory cell is held to a logic low value while an address signal of the memory cell is allowed to be asserted to a logic high value in conjunction with activating a power supply that provides operational power to the IC. Next, the address input to the memory cell ramps up to full logic high value, while the regulated power supply to the memory cell array is held low. The regulated power supply then ramps up to an operational level to bias the memory cell into a known logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.