Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements
US7783911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2006 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Nov 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.