Skew lots for IC oscillators and other analog circuits
US7784004B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2005 |
| Grant date | Aug 24, 2010 |
| Priority date | — |
| Expiry date | Sep 29, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Integrated circuits, key components in thousands of products, frequently include thousands and even millions of microscopic transistors and other electrical components. Because of difficulties and costs of fabricating these circuits, circuit designers sometimes ask fabricators to produce skew lots for testing and predicting manufacturing yield. However, conventional skew lots for CMOS circuits, which are based on increasing or decreasing transistor transconductance, are not very useful in testing certain types of analog circuits, such as oscillators. Accordingly, the present inventors developed a new type of skew lot, based on increasing or decreasing gate-to-source capacitance of transistors, or more generally a transistor characteristic other than transconductance. This new type of skew lot is particularly suitable for simulating, testing, and/or making yield predictions for oscillators and other CMOS analog circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.