Tapered edge exposure for removal of material from a semiconductor wafer
US7786012B2 · kind B2 · utility
1Cited by
1References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 12, 2007 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Sep 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor wafer edge exposure process as described herein employs a photoresist exposure step that exposes photoresist material to radiation having a gradient intensity profile near the outer edge of the wafer. The gradient intensity profile creates a tapered outer edge in the developed photoresist material, which in turn creates a tapered outer edge in the underlying target material after etching. Different gradient intensity profiles can also be used for subsequent layers of material. The resulting tapered edge profile of the wafer is resistant to edge peeling and flaking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.