Utilizing inverse reactive ion etching lag in double patterning contact formation
US7786017B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2009 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Sep 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Solutions for solutions for utilizing Inverse Reactive Ion Etching lag in double patterning contact formation are disclosed. In one embodiment, a method includes providing a CMOS device including: an NMOS device having an NMOS gate and a PMOS device having a PMOS gate; a shallow trench isolation located between the NMOS device and the PMOS device; and an inter-level dielectric located over the NMOS device, the PMOS device and the shallow trench isolation; performing a double-patterning etch process on the CMOS device under conditions causing inverse reactive ion etching lag, the performing including forming a first opening, a second opening and a third opening, the second opening being wider than the first opening, and the third opening being contiguous with the second opening; and forming a first contact in the first opening and forming a second contact in both of the second opening and the third opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.