Chip capacitive coupling
US7786592B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Aug 31, 2010 |
| Priority date | — |
| Expiry date | Apr 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.